Job description
Internship: 12-month
The task assignments will be purely technical in the areas of System Verilog, Verification, VMM or UVM Methodology.
Qualifications:
Should be a BE/BTech/ME/M.Tech Graduate with Electronics & Communication
Engineering or Electrical & Electronics Engineering or VLSI engineering or any other equivalent courses
Should have basic knowledge of Verilog/VHDL
Should have strong knowledge in Digital logic
Internship: 12-month
The task assignments will be purely technical in the areas of System Verilog, Verification, VMM or UVM Methodology.
Qualifications:
Should be a BE/BTech/ME/M.Tech Graduate with Electronics & Communication
Engineering or Electrical & Electronics Engineering or VLSI engineering or any other equivalent courses
Should have basic knowledge of Verilog/VHDL
Should have strong knowledge in Digital logic
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