Very Urgent Job Opening for ASIC Verification Engineer / Senior Engineer for an MNC.
Job Location: Bangalore / Ahmadabad.
Experience: 4- 10 years.
Notice Period: 30 - 45 days MAX.
At-least 1.5 years of experience in System Verilog HVL.
At-least 1 year of experience in OVM/UVM/VMM/Test Harness.
Experience in developing test and coverage plan and Verification environment.
Knowledge of industry standard protocols like Ethernet, PCIe, MIPI, AXI-AHB Bus etc. will be added advantage.
Please reply with your updated profile to srinivas.rao@techsysglobal.com
Job Location: Bangalore / Ahmadabad.
Experience: 4- 10 years.
Notice Period: 30 - 45 days MAX.
At-least 1.5 years of experience in System Verilog HVL.
At-least 1 year of experience in OVM/UVM/VMM/Test Harness.
Experience in developing test and coverage plan and Verification environment.
Knowledge of industry standard protocols like Ethernet, PCIe, MIPI, AXI-AHB Bus etc. will be added advantage.
Please reply with your updated profile to srinivas.rao@techsysglobal.com
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